Soft Microprocessor Core Dengan Pipeline Lima Tahap Berdasarkan Risc-V Base Integer Instruction Set Architecture Dalam Vhdl

Phangestu, Aaron Elson (2022) Soft Microprocessor Core Dengan Pipeline Lima Tahap Berdasarkan Risc-V Base Integer Instruction Set Architecture Dalam Vhdl. Other thesis, Institut Teknologi Sepuluh Nopember.

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Abstract

Teknologi proprietary dengan perizinan yang rumit saat ini mendominasi industri mikroprosesor. Akibatnya, pengembang perangkat keras harus mencari alternatif sumber terbuka yang tersedia secara bebas. Dalam Tugas Akhir ini, penulis membahas implementasi inti prosesor lunak dengan pipeline lima tahap. Processor core menggunakan Base Integer Instruction Set Architecture RISC-V RV32I. RISC-V adalah ISA standar terbuka yang tersedia secara bebas untuk digunakan dan dimodifikasi. Untuk mengimplementasikan inti prosesor, penulis mengikuti metodologi desain FPGA. Pertama, penulis mengimplementasikan spesifikasi desain dengan Bahasa Deskripsi Perangkat Keras VHDL. Kemudian, penulis mensimulasikan desain di lingkungan simulasi ModelSim. Setelah verifikasi, penulis menganalisis penggunaan sumber daya, jalur kritis, dan frekuensi maksimum prosesor, lalu mengunggah inti prosesor ke Cyclone IV EP4CE6E22C FPGA yang sebenarnya. Inti CPU penulis berhasil menjalankan semua instruksi RV32I, kecuali instruksi FENCE, ECALL, dan CSR. Inti prosesor yang diusulkan berjalan pada 2115 LUT, 558 flip-flop, dan 67.608 bit memori, dengan frekuensi maksimum 62,95 MHz.
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Proprietary technologies with complicated licensing currently dominate the microprocessor industry. As a result, we must seek out a freely available, open-source alternative. In this paper, we discussed the implementation of a five-stage pipelined soft processor core. The core uses the RISC-V RV32I Base Integer Instruction Set Architecture. RISC-V is an open standard ISA that is freely available to use and modify. To implement our processor core, we followed the FPGA design methodology. First, we implemented the design specification with the VHDL Hardware Description Language. Then, we simulated the design in the ModelSim simulation environment. Following the verification, we analyzed the resource usage, critical path, and maximum frequency of the processor, then uploaded the processor core to an actual Cyclone IV EP4CE6E22C FPGA. Our CPU core successfully executed all the RV32I instructions, except FENCE, ECALL, and CSR instructions. The proposed processor core runs on 2115 LUTs, 558 flip-flops, and 67,608 memory bits, with a maximum frequency of 62.95 MHz.

Item Type:	Thesis (Other)
Additional Information:	RSKom 621.391 6 Pha s-1 2022
Uncontrolled Keywords:	RISC-V, RV32I, FPGA, VHDL, soft processor core, pipeline lima tahap. RISC-V, RV32I, FPGA, VHDL, soft processor core, five-stage pipeline.
Subjects:	Q Science > QA Mathematics > QA75 Electronic computers. Computer science. EDP
Divisions:	Faculty of Intelligent Electrical and Informatics Technology (ELECTICS) > Computer Engineering > 90243-(S1) Undergraduate Thesis
Depositing User:	Mr. Marsudiyana -
Date Deposited:	17 Jun 2026 02:46
Last Modified:	17 Jun 2026 02:46
URI:	http://repository.its.ac.id/id/eprint/133841

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