Perancangan AI Accelerator Berbasis Arsitektur RISC-V untuk Klasifikasi Spektrum Fluorescence di FPGA

Fadhilia, Farsya Raisah (2026) Perancangan AI Accelerator Berbasis Arsitektur RISC-V untuk Klasifikasi Spektrum Fluorescence di FPGA. Masters thesis, Institut Teknologi Sepuluh Nopember.

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Abstract

Perkembangan Artificial Neural Network (ANN) membuka peluang pengolahan data spektrum fluorescence untuk klasifikasi kontaminan tanah secara lebih cepat dan otomatis. Namun, implementasi sebelumnya berbasis ESP32 masih memiliki keterbatasan komputasi dan memori, sedangkan pendekatan cloud computing membutuhkan bandwidth besar, menimbulkan latensi, dan kurang mendukung portabilitas sistem di lapangan. Oleh karena itu, diperlukan solusi edge AI yang mampu menjalankan inferensi secara lokal, mandiri, dan efisien. Penelitian ini merancang AI accelerator berbasis arsitektur RISC-V untuk klasifikasi spektrum fluorescence pada FPGA. Implementasi dilakukan melalui FPGA flow berbasis VexRiscv pada board Terasic DE10-Lite, sedangkan ASIC flow berbasis Caravel menggunakan OpenLane digunakan sebagai validasi dan pembanding. Pada sistem FPGA, VexRiscv berperan sebagai unit kontrol, sedangkan Neural Network Accelerator (NNA) fixed-point berperan sebagai unit komputasi inferensi. Model ANN memiliki struktur 6 input, tiga hidden layer, dan 3 output kelas. NNA diintegrasikan sebagai peripheral memory-mapped I/O (MMIO), sehingga firmware dapat menulis input, mengaktifkan inferensi, membaca status, mengambil hasil klasifikasi, dan mencatat jumlah siklus eksekusi. Hasil pengujian FPGA menunjukkan bahwa simulasi single-sample menghasilkan output class 1 dengan latency 3.385 cycles atau 84,625 µs pada clock internal 40 MHz. Regression 10 sampel menghasilkan pass count 10, fail count 0, all pass 1, dan total cycle count 33.850 cycles. Hasil sintesis Quartus menunjukkan penggunaan 19.368 logic elements, 11.634 registers, Fmax 42,85 MHz, serta setup dan hold slack positif. Pada jalur ASIC, NNA divalidasi melalui 50 sampel uji dengan mismatch count 0, pass rate 100%, dan observed latency 21 cycles atau 420 ns pada clock 50 MHz. Implementasi OpenLane menghasilkan standard-cell area 0,2626 mm² dan timing clean pada 50 MHz. Perbandingan performa menunjukkan bahwa eksekusi CPU tanpa NNA pada satu layer membutuhkan 172.851 cycles atau 4,321 ms, sekitar 51,06 kali lebih banyak siklus dibandingkan pendekatan CPU dengan NNA. Dengan demikian, AI accelerator berbasis RISC-V dan MMIO berhasil mendukung inferensi ANN lokal secara lebih efisien untuk klasifikasi spektrum fluorescence kontaminan tanah.
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The development of Artificial Neural Networks (ANNs) enables faster and more automated fluorescence spectrum processing for soil contaminant classification. However, previous ESP32-based implementations still have limitations in computation and memory, while cloud-based approaches require high bandwidth, introduce latency, and reduce field portability. Therefore, an edge-AI solution is needed to perform inference locally, independently, and efficiently. This study designs a RISC-V-based AI accelerator for fluorescence spectrum classification on FPGA. The main implementation uses a VexRiscv-based FPGA flow on the Terasic DE10-Lite board, while a Caravel-based ASIC flow using OpenLane is used as a validation and implementation comparison. In the FPGA system, VexRiscv acts as the control unit and the fixed-point Neural Network Accelerator (NNA) performs ANN inference. The NNA is integrated as a memory-mapped I/O (MMIO) peripheral, allowing the firmware to write inputs, start inference, read status, retrieve the output class, and record execution cycles. In the ASIC flow, the NNA core is connected to Caravel through an MMIO-based Wishbone wrapper and implemented using OpenLane. FPGA validation shows that the single-sample simulation produces output class 1 with 3,385 cycles or 84.625 µs at a 40 MHz internal clock. The 10-sample regression test achieves pass count 10, fail count 0, all pass 1, and total cycle count 33,850 cycles. Quartus synthesis results show 19,368 logic elements, 11,634 registers, Fmax 42.85 MHz, and positive setup and hold slack. ASIC validation shows 50 passing samples, mismatch count 0, pass rate 100%, and observed latency 21 cycles or 420 ns at 50 MHz. OpenLane implementation produces a standard-cell area of 0.2626 mm² and timing-clean operation at 50 MHz. The comparison shows that ASIC has lower latency, while FPGA provides flexibility for hardware prototyping. CPU execution without NNA on one layer requires 172,851 cycles or 4.321 ms, about 51.06 times more cycles than the CPU with NNA approach. Therefore, the proposed RISC-V and MMIO-based AI accelerator successfully supports efficient local ANN inference for fluorescence spectrum classification.

Item Type:	Thesis (Masters)
Uncontrolled Keywords:	AI Accelerator, RISC-V, FPGA, VexRiscv, NNA, MMIO, Spektrum Fluorescence, edge-AI. ================================================================ AI Accelerator, RISC-V, FPGA, VexRiscv, NNA, MMIO, Fluorescence Spectrum, edge-AI.
Subjects:	T Technology > TK Electrical engineering. Electronics Nuclear engineering > TK7878 Electronic instruments T Technology > TK Electrical engineering. Electronics Nuclear engineering > TK7888.3 Digital computers T Technology > TK Electrical engineering. Electronics Nuclear engineering > TK7895.G36 Field programmable gate arrays--Design and construction.
Divisions:	Faculty of Intelligent Electrical and Informatics Technology (ELECTICS) > Electrical Engineering > 20101-(S2) Master Thesis
Depositing User:	Farsya Ra~isah Fadhilia
Date Deposited:	16 Jul 2026 08:42
Last Modified:	16 Jul 2026 08:42
URI:	http://repository.its.ac.id/id/eprint/135251

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