Perancangan Kalibrasi Digital Background pada SAR ADC Berbasis Algoritma Least Mean Square

Ashari, Ilyasa' Sirojuddin Syafiq (2026) Perancangan Kalibrasi Digital Background pada SAR ADC Berbasis Algoritma Least Mean Square. Other thesis, Institut Teknologi Sepuluh Nopember.

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Abstract

Arsitektur successive approximation register (SAR) ADC banyak digunakan pada sistem akuisisi data berdaya rendah karena memiliki efisiensi energi yang tinggi dan kompleksitas rangkaian yang relatif rendah. Kinerja dinamis SAR ADC dapat menurun akibat mismatch kapasitansi pada capacitive digital-to-analog converter (CDAC), efek resistansi dan kapasitansi parasitik, serta nonidealitas rangkaian. Penelitian ini merancang kalibrasi digital background pada SAR ADC berbasis algoritma least mean square (LMS) untuk mengurangi pengaruh eror CDAC. Rancangan kalibrasi digital diimplementasikan pada tingkat register transfer level (RTL) menggunakan Verilog. Metode kalibrasi menggunakan urutan perturbasi ganda yang terdiri atas konversi B+, fase restore, konversi B-, perhitungan eror, dan pembaruan bobot digital. Rancangan RTL diverifikasi menggunakan testbench dan pengamatan waveform, kemudian diintegrasikan dengan rangkaian SAR ADC acuan pada Cadence untuk simulasi transien. Data keluaran ADC diekspor dan dianalisis menggunakan FFT untuk memperoleh metrik SNR, SFDR, SINAD, dan ENOB. Hasil simulasi menunjukkan bahwa SNR dan SINAD meningkat dari 37.592359 dB menjadi 40.951938 dB, SFDR meningkat dari 41.4732285 dBc menjadi 43.430379 dBc, dan ENOB meningkat dari 5.95 bit menjadi 6.5094884 bit. Hasil tersebut menunjukkan bahwa kalibrasi digital background berbasis LMS mampu meningkatkan kinerja dinamis SAR ADC pada kondisi simulasi yang dilakukan
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The successive approximation register (SAR) ADC architecture is widely used in lowpower data acquisition systems because of its high energy efficiency and relatively low circuit complexity. The dynamic performance of a SAR ADC can be degraded by capacitor mismatch in the capacitive digital-to-analog converter (CDAC), parasitic resistance and capacitance effects, and circuit nonidealities. This work designs a background digital calibration for a SAR ADC based on the least mean square (LMS) algorithm to reduce the effect of CDAC error. The digital calibration circuit is implemented at the register transfer level (RTL) using Verilog. The calibration method uses a double-perturbation sequence consisting of B+ conversion, restore phase, B- conversion, error calculation, and digital weight update. The RTL design is verified using a testbench and waveform observation, then integrated with a reference SAR ADC circuit in Cadence for transient simulation. The ADC output data are exported and analyzed using FFT to obtain SNR, SFDR, SINAD, and ENOB metrics. The simulation results show that SNR and SINAD increase from 37.592359 dB to 40.951938 dB, SFDR increases from 41.4732285 dBc to 43.430379 dBc, and ENOB increases from 5.95 bits to 6.5094884 bits. These results show that the LMS-based background digital calibration improves the dynamic performance of the SAR ADC under the simulated condition.

Item Type:	Thesis (Other)
Uncontrolled Keywords:	CDAC, Kalibrasi Digital Background, LMS, SAR ADC, SNR, SFDR, SINAD, ENOB, Verilog RTL.
Subjects:	T Technology > TK Electrical engineering. Electronics Nuclear engineering > TK5102.9 Signal processing.
Divisions:	Faculty of Intelligent Electrical and Informatics Technology (ELECTICS) > Electrical Engineering > 20201-(S1) Undergraduate Thesis
Depositing User:	Ilyasa' Sirojuddin Syafiq Ashari
Date Deposited:	27 Jul 2026 08:28
Last Modified:	27 Jul 2026 08:28
URI:	http://repository.its.ac.id/id/eprint/137763

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