Hardware Implementation of Stream Ciphers: Grain and F-FCSR-H

Muhtadin, Muhtadin (2009) Hardware Implementation of Stream Ciphers: Grain and F-FCSR-H. Masters thesis, Institut Teknologi Sepuluh Nopember.

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Abstract

eSTREAM is an EU project aiming to select and identify various new stream ciphers. The submissions to eSTREAM fall into two categories: Profile 1 (for software applications) and Profile 2 (for hardware applications). The Grain family and F-FCSR-H are two candidates in Profile 2. This thesis describes the implementation of the two algorithms—Grain, Grain-128, and F-FCSR-H—into VHDL code with subsequent migration onto the FPGA development board Altera DE2-70, using Quartus II Web Edition. Implementations of Grain are compared across different degrees of parallelization, from 1 bit to 32 bits per clock cycle. F-FCSR-H has a fixed 8-bit-wide execution. In our DE2-70 implementation, Grain-128 yields the highest throughput of 6526.72 Mbps for the 32-bit case. Finally, we conclude that Grain and Grain-128 are more suitable for hardware implementation than F-FCSR-H, as they require fewer resources while providing higher throughput than F-FCSR-H.

Item Type:	Thesis (Masters)
Uncontrolled Keywords:	cryptography, stream cipber, VHDL, FPGA
Subjects:	T Technology > TK Electrical engineering. Electronics Nuclear engineering > TK5102.94 Cryptographic techniques
Divisions:	Faculty of Electrical Technology > Electrical Engineering > 20101-(S2) Master Thesis
Depositing User:	magang .
Date Deposited:	28 Sep 2026 08:39
Last Modified:	28 Sep 2026 08:39
URI:	http://repository.its.ac.id/id/eprint/144992

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