Analisis Kinerja Robustness pada Desain Antena Full Array Berbasis Subarray

Pertiwi, Titis Cahya (2022) Analisis Kinerja Robustness pada Desain Antena Full Array Berbasis Subarray. Masters thesis, Institut Teknologi Sepuluh Nopember.

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Abstract

Metode desain phased array dengan sudut pemindaian lebar yang terdiri dari beberapa subarray terintegrasi untuk mengurangi masalah scan loss dan side lobe level (SLL) sebelumnya telah dilaporkan dalam literatur. Dalam kondisi nyata, antena bekerja terus menerus 24 jam sehari, 7 hari seminggu, sehingga rentan terhadap kerusakan. Ada banyak jenis kerusakan, seperti terputusnya koneksi (feeder), elemen rusak, atau tidak berfungsi elemen. Oleh sebab itu analisis robustness dalam makalah perlu dilakukan agar mengetahui seberapa robust full array tersebut. Penelitian ini membahas robustness dengan kondisi subarray rusak, per elemen rusak dan sensitivitas error pada digital phase shifter yang terbagi menjadi beberapa case. Kerusakan ini terjadi apabila 1 subarray atau 1 subarray lebih akan mengalami penurunan kinerja full array ditandai dengan perubahan nilai Dmax, peak side lobe level ( PSLL), first side lobe level (FSLL) , dan scan loss. Hal tesebut juga berpengaruh saat elemen pada subarray rusak. Analisis juga dilakukan ketika digital phase shifter digunakan. Penelitian ini menggunakan digital phase shifter yaitu 2 bit, 4 bit, 5 bit, 6 bit, 8 bit, 9 dan 10 bit. Dalam penelitian ini dihasilkan kinerja antena full array tidak robust terjadi saat 4 subarray tipe 4b dengan 12 elemen mengalami kerusakan, dimana memiliki nilai PSLL dan FSLL besar yaitu -12.35 dB pada scan 60° apabila dibandingkan dengan kondisi bagus dan uniform linear array (ULA). Dmax mengalami penurunan 0.25 dBi setiap kerusakan 1 elemen dibandingkan dengan tidak terjadi kerusakan pada full array. Pengunaan digital phase shifter didapatkan bahwa semakin besar jumlah bit yang digunakan semakin bagus pola directivity. Selain itu pada penelitian ini menggunakan digital phase shifter 8 bit memiliki arah scan yang tepat dengan scan loss compensation (SLC) kecil sebesar -0.41 dB saat scan 35 ° dan 60° sebesar -3.89 dB dan nilai PSLL sebesar -13.37 dB dan FSLL sebesar -13.37 dB saat scan 60°. Kondisi yang disarankan dalam penelitian ini adalah pada saat bit lebih dari 9 bit digital phase shifter yang digunakan. Dimana pada 9 bit Dmax sebesar 19.61 dBi, PSLL sebesar -13.16 dB dan FSLL sebesar -20.27 dB pada sudut scan maksimal 60° dan memiliki sensitivitas error kecil.
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A phased array design method with wide scanning angles consisting of multiple integrated subarrays to reduce scan loss and side lobe level (SLL) problems has previously been reported in the literature. Under real conditions, the antenna works continuously 24 hours a day, 7 days a week, making it vulnerable to damage. There are many types of damage, such as disconnection of the connection (feeder), broken elements, or non-functioning elements. Therefore, the robustness analysis in this paper needs to be carried out in order to find out how robust the full array is. This study discusses the robustness of the damaged subarray condition, damaged per element and error sensitivity of the digital phase shifter which is divided into several cases. This damage occurs when 1 subarray or 1 more subarray will experience a decrease in full array performance marked by a change in the value of Dmax, peak side lobe level (PSLL), first side lobe level (FSLL) , and scan loss. It also has an effect when the elements in the subarray are corrupted. Analysis was also carried out when digital phase shifters were used. This study uses digital phase shifters, namely 2 bits, 4 bits, 5 bits 6 bits, 8 bits, 9 and 10 bits. In this study, the performance of full array antennas was not robust when 4 type 4b subarrays with 12 elements were damaged, which had large PSLL and FSLL values of -12.35 dB at 60° scan when compared to good conditions and uniform linear arrays (ULA). Dmax has decreased by 0.25 dBi for every 1 element damage compared to no damage to the full array. Using a digital phase shifter, it is found that the greater the number of bits used, the better the directivity pattern. In addition, in this study using an 8-bit digital phase shifter has the right scan direction with a small scan loss compensation (SLC) of -0.41 dB when scanning 35° and 60° of -3.89 dB and a PSLL value of -13.37 dB and an FSLL of - 13.37 dB at 60° scan. The condition suggested in this study is when bits more than 9 bits digital phase shifter is used. Where at 9 bit Dmax is 19.61 dBi, PSLL is -13.16 dB and FSLL is -20.27 dB at a maximum scan angle of 60° and has a small error sensitivity.

Item Type:	Thesis (Masters)
Uncontrolled Keywords:	robustness, subarray, digital phase shifter, PSLL, FSLL
Subjects:	T Technology > T Technology (General) > T57.62 Simulation
Divisions:	Faculty of Intelligent Electrical and Informatics Technology (ELECTICS) > Electrical Engineering > 20101-(S2) Master Thesis
Depositing User:	Titis Cahya Pertiwi
Date Deposited:	25 Jan 2023 14:32
Last Modified:	25 Jan 2023 14:32
URI:	http://repository.its.ac.id/id/eprint/95639

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