Desain Tegangan Referensi Celah Pita pada Rangkaian Terintegrasi Berbasis Skywater CMOS 130nm

Falah, Gilang Fajrul (2024) Desain Tegangan Referensi Celah Pita pada Rangkaian Terintegrasi Berbasis Skywater CMOS 130nm. Other thesis, Institut Teknologi Sepuluh Nopember.

Text 5022201231-Undergraduate_Thesis.pdf - Accepted Version Restricted to Repository staff only until 1 October 2026. Download (3MB) | Request a copy

Abstract

Rangkaian terintegrasi memegang peran krusial dalam evolusi teknologi elektronika. Namun, perubahan suhu dapat memengaruhi responsnya secara signifikan, menekankan kebutuhan akan tegangan referensi yang stabil agar rangkaian terintegrasi tetap beroperasi dengan optimal. Penelitian ini fokus pada pengembangan rangkaian tegangan referensi celah pita (band gap) yang dapat diimplementasikan pada rangkaian terintegrasi. Metode ini melibatkan variasi suhu dan suplai sebagai salah satu parameter desain untuk mencapai kinerja optimal rangkaian di berbagai kondisi operasional. Proses perancangan melibatkan studi literatur, pembuatan desain skematik, pembuatan tata letak, dan mencocokkan tata letak dengan skematik. Selanjutnya, pengujian post-layout simulation dilakukan untuk memvalidasi kinerja rangkaian terintegrasi dalam kondisi mendekati keadaan asli sebelum masuk tahap manufaktur. Hasil penelitian ini didapatkan bahwa pengujian post-layout simulation dapat berjalan dengan pendekatan transien dan memberikan nilai yang diinginkan yaitu Vref 1.2193V, PSRR 74dB, koefisien suhu 13ppm/C, dan line regulation 0.12% dan siap untuk dicetak pada kesempatan Tinytapeout maupun MinGW oleh Efabless.
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Integrated circuits play a crucial role in the evolution of electronics technology. However, temperature changes can significantly affect its response, emphasizing the need for a stable reference voltage for the integrated circuit to continue operating optimally. This research focuses on the development of a band gap reference voltage circuit that can be implemented in an integrated circuit. This method involves temperature and supply variations as one of the design parameters to achieve optimal performance of the circuit under various operating conditions. The designing process involves studying literature, creating schematic designs, creating layouts, and matching layouts to schematics. Furthermore, post-layout simulation testing is carried out to validate the performance of the integrated circuit in conditions close to the original state before entering the manufacturing stage. The results of this study were obtained that the post-layout simulation test could run with a transient approach and provide the desired values, namely Vref 1.2193V, PSRR 74dB, temperature coefficient 13ppm/C, and line regulation 0.12% and ready to be printed on Tinytapeout and MinGW by Efabless.

Item Type:	Thesis (Other)
Uncontrolled Keywords:	Band Gap Reference, CTAT, PTAT, open-source, Rangkaian Terintegrasi, CMOS, Integrated Circuit
Subjects:	T Technology > TK Electrical engineering. Electronics Nuclear engineering > TK2851 Voltage regulators.
Divisions:	Faculty of Intelligent Electrical and Informatics Technology (ELECTICS) > Electrical Engineering > 20201-(S1) Undergraduate Thesis
Depositing User:	Gilang Fajrul Falah
Date Deposited:	04 Sep 2024 08:14
Last Modified:	04 Sep 2024 08:14
URI:	http://repository.its.ac.id/id/eprint/110973

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