Stefanus, Yohanes (2025) Desain DAC Tersegmentasi Parsial 10-Bit Dengan Interpolasi Kontrol Arus Variabel Untuk Koreksi Gamma Pada Active-Matrix LCD Menggunakan Teknologi CMOS 130 NM. Other thesis, Institut Teknologi Sepuluh Nopember.
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Abstract
Penggunaan Active-Matrix Liquid-Crystal Display (AMLCD) berkembang sangat pesat dalam industri layar elektronik. Akan tetapi, liquid-crystal (LC) memiliki hubungan yang non-linier antara transmitansi terhadap tegangan yang diberikan. Hal ini menyebabkan gambar yang tertampil terlihat kusam dan berkurangnya tingkat keakuratan warna pada panel LCD. Kendala tersebut dapat dikompensasi dengan koreksi gamma pada tingkat perangkat keras dengan mendesain sebuah Digital-to-Analog Converter (DAC) non-linier. Penelitian ini berfokus pada desain rangkaian terintegrasi DAC tersegmentasi parsial 10-bit berkecepatan 100 kHz untuk mengontrol panel LCD perangkat mobile dengan 1.073.741.842 warna dengan resolusi FHD (1920 × 1080 px) berkecepatan 60 FPS. Arsitektur DAC yang digunakan berjenis tersegmentasi parsial (partially segmented) dengan 6-bit thermometer-coded R-DAC dan 4-bit binary weighted DAC-embedded op-amp. Arsitektur tersebut dipilih karena dapat menyediakan ukuran chip yang jauh lebih kecil dari RDAC konvensional dan sekaligus memiliki fitur interpolasi kontrol arus variabel untuk koreksi gamma on chip. Desain IC dilakukan menggunakan teknologi CMOS 130 nm dari SkyWater. DNL dan INL terbesar yang dihasilkan pada pre
layout simulation (PRESIM) sebesar 0,661 LSB dan 1,299 LSB, sedangkan pada post-layout simulation (POSIM) sebesar 2,22 LSB dan 37,4 LSB. DAC ini menghasilkan SFDR sebesar 19,549 dB dan settling time sebesar 2,25
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The use of Active-Matrix Liquid-Crystal Displays (AMLCDs) has grown rapidly in the electronic display industry. However, liquid crystal (LC) has a nonlinear relationship between transmittance and the applied voltage, which causes displayed images to appear dull and reduces color accuracy on LCD panels. This issue can be compensated through hardware-level gamma correction by designing a nonlinear Digital-to-Analog Converter (DAC). This study focuses on the design of a 10-bit, partially segmented integrated DAC operating at 100 kHz, intended to control mobile device LCD panels supporting 1,073,741,842 colors at Full HD resolution (1920 × 1080 pixels) at 60 FPS. The DAC uses a partially segmented architecture, consisting of a 6-bit thermometer-coded R-DAC and a 4-bit binary-weighted DAC embedded in an operational amplifier. This architecture was chosen because it offers a significantly smaller chip area than conventional 10-bit R-DACs, while also featuring variable current interpolation for on-chip gamma correction. The IC design is implemented using 130 nm CMOS technology from SkyWater. In pre-layout simulations (PRESIM), the maximum Differential Non-Linearity (DNL) and Integral Non-Linearity (INL) were 0.661 LSB and 1.299 LSB, respectively. In post-layout simulations (POSIM), these values increased to 2.22 LSB and 37.4 LSB. The DAC achieved a Spurious-Free Dynamic Range (SFDR) of 19.549 dB, with settling times of 2.25 μs (PRESIM) and 2.375 μs (POSIM), respectively. The designed DAC occupies a chip area of 13,907.916 μm², which is 26.262% smaller than that of a conventional 10-bit R-DAC.
Item Type: | Thesis (Other) |
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Uncontrolled Keywords: | Digital-to-Analog Converter (DAC), Interpolasi Tegangan, Koreksi Gamma, Rail-to-Rail Op-Amp, Display Driver ==================================================================================== Digital-to-Analog Converter (DAC), Voltage Interpolation, Gamma Correction, Rail-to-Rail Op-Amp, Display Driver |
Subjects: | T Technology > TK Electrical engineering. Electronics Nuclear engineering > TK7878 Electronic instruments |
Divisions: | Faculty of Intelligent Electrical and Informatics Technology (ELECTICS) > Electrical Engineering > 20201-(S1) Undergraduate Thesis |
Depositing User: | Yohanes Stefanus |
Date Deposited: | 27 Jul 2025 15:12 |
Last Modified: | 27 Jul 2025 15:12 |
URI: | http://repository.its.ac.id/id/eprint/122213 |
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