Desain Low Drop-out Regulator (LDO) dengan Power Supply Rejection Ratio Tinggi dan Kapasitansi dalam Chip Kecil pada Teknologi CMOS

Wardhana, Kandias Radista (2026) Desain Low Drop-out Regulator (LDO) dengan Power Supply Rejection Ratio Tinggi dan Kapasitansi dalam Chip Kecil pada Teknologi CMOS. Other thesis, Institut Teknologi Sepuluh Nopember.

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Abstract

Kebutuhan sirkuit terpadu terhadap catu daya yang teratur dan rendah noise mendorong pengembangan low dropout regulator (LDO) dengan PSRR yang tinggi. Tugas akhir ini bertujuan merancang dan mengarakterisasi LDO yang terdiri dari bias network, error amplifier, voltage damper, transistor PMOS sebagai pass element, kapasitor kompensasi, dan jaringan resistor umpan balik. Metode yang digunakan meliputi perancangan skematik, simulasi pra tata letak, pembuatan tata letak, serta simulasi pasca tata letak pada variasi corner FF, SS, dan TT untuk mengevaluasi regulasi, PSRR, dan respons transien. Hasil pra tata letak menunjukkan rentang line regulation sebesar 0,18–0,40 mV, PSRR pada 1 kHz sebesar 61,56–62,33 dB, respons load transient sebesar 31,53–32,54 mV, dan respons line transient sebesar 4,30–6,06 mV. Penggunaan voltage damper menurunkan RMSdeviation pada pengujian line transient sebesar 34,20% pada corner FF dan 35,75% pada corner SS. Namun, hasil pasca tata letak menunjukkan degradasi performa akibat parasitik, dengan rata-rata PSRR menjadi-16,48 dB, respons load transient meningkat menjadi 679,01–857,16 mV, dan respons line transient berada pada 8,67–12,28 mV. Dengan demikian, rancangan LDO telah menunjukkan fungsi regulasi dasar pada tahap pra tata letak, tetapi optimasi tata letak pada node sensitif, jalur umpan balik, dan jalur keluaran masih diperlukan untuk meningkatkan PSRR dan respons keluaran.
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The need of integrated circuits for regulated and low-noise power supplies drives the development of low dropout regulators (LDOs) with high PSRR. This final project aims to design and characterize an LDO consisting of a bias network, error amplifier, voltage damper, PMOS transistor as a pass element, compensation capacitor, and resistive feedback network. The method includes schematic design, pre-layout simulation, layout implementation, and post-layout simulation under FF, SS, and TT process corners to evaluate regulation, PSRR, and transient response. The pre-layout results show a line-regulation range of 0.178–0.403 mV, PSRR at 1 kHz of 61.555–62.332 dB, load-transient response of 31.529–32.539 mV, and line-transient response of 4.301–6.058 mV. The use of the voltage damper reduces the RMS deviation in the line-transient test by 34.20% at the FF corner and 35.75% at the SS corner. However, the post-layout results show performance degradation caused by parasitics, with the average PSRR becoming-16.483 dB, the load-transient response increasing to 679.008–857.156 mV, and the line-transient response ranging from 8.669–12.278 mV. Therefore, the designed LDO has demonstrated basic regulation functionality at the pre-layout stage, but layout optimization on sensitive nodes, feedback paths, and output paths is still required to improve PSRR and output response.

Item Type:	Thesis (Other)
Uncontrolled Keywords:	Sirkuit Terpadu, LDO, PSRR, voltage damper, simulasi, respons transien Integrated Circuit, LDO, PSRR, voltage damper, simulation, transient response
Subjects:	T Technology > TK Electrical engineering. Electronics Nuclear engineering > TK2851 Voltage regulators.
Divisions:	Faculty of Intelligent Electrical and Informatics Technology (ELECTICS) > Electrical Engineering > 20201-(S1) Undergraduate Thesis
Depositing User:	Kandias Radista Wardhana
Date Deposited:	20 Jul 2026 07:35
Last Modified:	20 Jul 2026 07:35
URI:	http://repository.its.ac.id/id/eprint/135721

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